1. Field of the Invention
The present invention relates to a semiconductor device and fabrication method. More particularly, the invention relates to a nonvolatile memory device and fabrication method.
This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 2006-102375, filed on Oct. 20, 2006, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
As semiconductor devices become more highly integrated, the planar surface area occupied by the patterns and components implementing such devices decreases. However, there are finite limits to similar reductions in the vertical height of these patterns and components. As a result, contemporary semiconductor devices are being fabricated with increasing vertical heights.
As a result of this phenomenon, some of the fabrication processes used to form highly integrated patterns having relatively large heights make use of high-energy plasma. Such processes often result in an accumulation of plasma ions and/or electrical charge on pattern elements and components. Such an accumulation of ions and charge can have detrimental effects on the overall performance characteristic transistors within the semiconductor device.
For example, in certain nonvolatile memory devices, programming and erase operations are performed via a tunnel insulating layer. High reliability of this tunnel insulating layer is essential to proper operation of the devices. Ions and/or charge accumulated on pattern elements and components may migrate into the tunnel insulating layer, thereby degrading its reliability and durability. The reliability and durability of the tunnel insulating layer influences the endurance, data retention and hot temperature storage properties of the constituent memory device. Therefore, any degradation in the reliability of the tunnel insulating layer (directly or indirectly) results in detrimental effects on the operation and durability of transistors.
FIGS. 1 through 3 are cross-sectional views illustrating a fabrication method for a conventional nonvolatile memory device.
Referring to FIG. 1, an active region (not shown) is defined on a semiconductor substrate 10. A gate insulating layer 12 and a floating gate layer 14 are stacked on the active region. A dielectric layer 22 and a control gate layer 24 are formed on floating gate layer 14, and a hard mask layer 26 is formed on control gate layer 24.
Referring to FIG. 2, hard mask layer 26, control gate layer 24 and dielectric layer 22 are sequentially patterned to form a hard mask pattern 26a, a control gate electrode 24a and an inter-gate dielectric layer 22a under the control gate electrode 24a which cross over the active region. Ions and/or charge may accumulate in floating gate layer 14 as well as control gate electrode 24a and inter-gate dielectric layer 22a during high-energy plasma fabrication processes. The accumulated ions and/or charge may migrate to and accumulate on gate insulating layer 12, thereby degrading the performances properties of gate insulating layer 12.
Referring to FIG. 3, floating gate layer 14 is etched using hard mask pattern 26a as an etch mask to form a floating gate 14a self-aligned with control gate electrode 24a. During this process, plasma ions and/or charge may further accumulate on floating gate 14a. As floating gate 14a is formed in electrical isolation on the active region, any ions and/or charge accumulated on floating gate 14a move towards semiconductor substrate 10 which has a relatively low voltage potential and become trapped by gate insulating layer 12. Trapped ions and/or charge interfere with control voltages applied to the various components of the constituent memory device.